Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!uunet!sco!seanf
From: seanf@sco.COM (Sean Fagan)
Newsgroups: comp.arch
Subject: Re: IBM RISC
Message-ID: <4973@scolex.sco.COM>
Date: 25 Feb 90 01:30:15 GMT
References: <9376@portia.Stanford.EDU> <192@zds-ux.UUCP> <1990Feb22.175120.12835@utzoo.uucp>
Reply-To: seanf@sco.COM (Sean Fagan)
Organization: The Santa Cruz Operation, Inc.
Lines: 18

In article <1990Feb22.175120.12835@utzoo.uucp> henry@utzoo.uucp (Henry Spencer) writes:
>Um, I haven't followed the details of the new IBM stuff, but my impression
>is that most of the "super-scalar" parallelism being touted is just
>parallelism between integer and floating-point operations, which both
>MIPS and SPARC have had from the beginning...

Not from what I've understood; it seems as if they have multiple functional
units on their chip.  Nice idea, of course:  Seymour Cray had it in the CDC
Cybers, decades ago (ob. Seymour plug 8-)), and so do MIPS chips, I believe
(although I'm not sure how many the MIPS chips have).

And, of course, the 8088 and 8087 could operate in parallel.  Frightening,
eh?

-- 
Sean Eric Fagan  | "Time has little to do with infinity and jelly donuts."
seanf@sco.COM    |    -- Thomas Magnum (Tom Selleck), _Magnum, P.I._
(408) 458-1422   | Any opinions expressed are my own, not my employers'.