Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!romp!auschs!awdprime!woan.austin.ibm.com!ron
From: ron@woan.austin.ibm.com (Ronald S. Woan/2100000)
Newsgroups: comp.arch
Subject: Re: IBM RISC
Keywords: what integer parallelism?
Message-ID: <1653@awdprime.UUCP>
Date: 26 Feb 90 23:05:00 GMT
References: <8064@pt.cs.cmu.edu> <7454@pdn.paradyne.com>
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In article <7454@pdn.paradyne.com>, alan@oz.nm.paradyne.com (Alan
Lovejoy) writes:
|> You forgot at least one possibility, which an IBM spokesman claims
|> just happens to be the real reason: the compilers have not yet been
|> updated to take any real advantage of the integer instruction
|> paralellism provided by the CPU.  Of course, some of the
|> paralellism (5 instructions/cycle max) is only available when FP
|> instructions are to be executed, but the same is true for most
|> other "superscalars" and/or "near superscalars" which are currently
|> available.  Expect integer benchmark performance to much more
|> closely resemble the claimed "MIPS" ratings when the new compilers
|> become available.

I must have missed something here... What integer unit parallelism?
From what I understand, the integer unit is a single pipeline (5?
stages), so it can never do better than one instruction/cycle. To get
five/cycle, you need two branches, float add, float mult, and integer
operation. Only an amazing compiler can schedule an application to use
this frequently.

						Ron

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