Path: utzoo!attcan!uunet!mcsun!ukc!inmos!braa!davidb
From: davidb@braa.inmos.co.uk (David Boreham)
Newsgroups: comp.arch
Subject: Re: Parity (was: Time between memory failure)
Message-ID: <4234@ganymede.inmos.co.uk>
Date: 27 Feb 90 18:27:00 GMT
References: <1911@sunquest.UUCP> <38420@apple.Apple.COM> <2102@crdos1.crd.ge.COM> <4139@ganymede.inmos.co.uk> <08b.02x48aub01@amdahl.uts.amdahl.com>
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Reply-To: davidb@inmos.co.uk (David Boreham)
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In article <08b.02x48aub01@amdahl.uts.amdahl.com> terry@amdahl.uts.amdahl.com (Lewis T. Flynn) writes:
>double bit error detection, and get real upset if they have to power their
>machines down for any reason. One system with which I was personally associated
>was booted for any reason only three times in 19 months and the processor was
>never powered down during that time.
>this subject might be (although I bet I could guess 8-).


Absolutely, this however does nothing for the argument for simple parity checking.
There you only get a red light on and a halted machine.
As I said in my original posting, the soft-error rates exhibited by modern
DRAMs are slow low that there are plenty of other similarly likely sources
of error in PCs and workstations and therefore I don't believe that parity 
is necessary in those kinds of machines.

If you have a Gbyte of DRAM then you should expect a soft error every year or so.
If you want to have a good chance of staying up for three months then you need
ECC on your DRAM. However, without all kinds of other redundancy you should not
expect the rest of your system to stay up for three months either.

David Boreham, INMOS Limited | mail(uk): davidb@inmos.co.uk or ukc!inmos!davidb
Bristol,  England            |     (us): uunet!inmos.com!davidb
+44 454 616616 ex 547        | Internet: davidb@inmos.com