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From: jxw@rods.ius.cs.cmu.edu (John Willis)
Newsgroups: comp.parallel
Subject: Re: Distributed Shared Memory
Summary: Philips effort
Message-ID: <8167@hubcap.clemson.edu>
Date: 26 Feb 90 19:35:30 GMT
Sender: fpst@hubcap.clemson.edu
Lines: 11
Approved: parallel@hubcap.clemson.edu

"Cache Coherence in Systems with Parallel Communication Channels and
Many Processors" is available from Philips Laboratories, 345 Scarborough
Road, Briarcliff Manor, NY 10510 as TR-88-013.  It describes a hardware/
PAL design for efficiently emulating shared-memory in the cache / memory
of a large, message-based multiprocessor using a distributed, single-ended,
linked list.

You might also keep an eye out for the Scalable Coherent Interface's
cache coherence protocol.

-John