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From: rusti@milk0.itstd.sri.com (Rusti Baker)
Newsgroups: comp.dcom.lans,comp.protocols.tcp-ip,comp.protocols.tcp-ip.ibmpc
Subject: Re: TCP Ethernet Throughput (AMD vs. Intel vs. Seeq)
Summary: request for information characterizing these chips
Keywords: Van Jacobson, Steve Bellovin
Message-ID: <29914@sparkyfs.istc.sri.com>
Date: 10 Feb 90 01:34:12 GMT
Expires: 1 Mar 90 08:00:00 GMT
References: <2447@ncr-sd.SanDiego.NCR.COM> <582@berlioz.nsc.com> <29000@amdcad.AMD.COM>
Sender: news@sparkyfs.istc.sri.com
Reply-To: rusti@milk0.itstd.sri.com.UUCP (Rusti Baker)
Organization: ITSTD
Lines: 8
Sender:Rusti Baker

I would be interested in seeing any type of discussion of 
the behaviour of the chips mentioned in this thread.

E.G. Clark, Jacobson et al provided this insight into the 
behavior of the LANCE in their June 1989 IEEE Comm.  article: 

"[the LANCE] locks up the memory bus during the transfer
thus stalling the processor"