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From: rusti@milk0.itstd.sri.com (Rusti Baker)
Newsgroups: comp.dcom.lans,comp.protocols.tcp-ip,comp.protocols.tcp-ip.ibmpc
Subject: Re: TCP Ethernet Throughput (AMD vs. Intel vs. Seeq)
Keywords: Van Jacobson, Steve Bellovin
Message-ID: <29931@sparkyfs.istc.sri.com>
Date: 12 Feb 90 20:40:33 GMT
Expires: 1 Mar 90 08:00:00 GMT
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Reply-To: rusti@milk0.itstd.sri.com.UUCP (Rusti Baker)
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Thanks to Mark Montgomery and George Robbins for clarification of the
problem of characterizing the performance of a chip set without considering
the interface/system.

>	Also if you'll re-read the article you'll see that what they
>	were saying was that the LANCE was "stalling" the cpu while
>	it did dma of the packet directly to memory.  Can't do that
>	with an XYZ chip.  Of course you could have the cpu do the
>	transfers or you could build a cache if you'd rather.
>				Mark

I was intrigued by the use of the word "stalling", versus "blocking" etc.
I had interpreted the remark in the article to mean that there was something
else going on (like the DMA had some other side effect).  Since the
authors did not elaborate, I was curious.