Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!rutgers!cbmvax!daveh
From: daveh@cbmvax.commodore.com (Dave Haynie)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: 50 MHz MC68040 capabilities?
Keywords: CPU DRAM 386
Message-ID: <9780@cbmvax.commodore.com>
Date: 22 Feb 90 08:44:53 GMT
References: <1129@mindlink.UUCP> <9691@cbmvax.commodore.com> <1013@metaphor.Metaphor.COM> <19411@grebyn.com> <100149@convex.convex.com>
Reply-To: daveh@cbmvax.cbm.commodore.com (Dave Haynie)
Organization: Commodore, West Chester, PA
Lines: 29

In article <100149@convex.convex.com> swarren@convex.com (Steve Warren) writes:
>In article <19411@grebyn.com> allen@grebyn.UUCP (Allen Farrington) writes:

>>The bottom line is that any SYSTEM which does not use a cache will be
>>limited to about 14MHz (70nS DRAM) memory execution.  Beware of

>Well, Hitachi has come out with 1 Mbit DRAMs with a 35 ns access time
>and 70 ns cycle time.  This would allow a zero-wait-state daughter-card
>to be designed for the 2630 without resorting to any fancy gymnastics.

That might would just do it, though with buffer delays even that could 
result in a required wait state without some interleaving.  

>There is no RAS or CAS on these chips.  The addr bus is not multiplexed.
>They have a static column mode and come in 1M X 1 & 256K X 4.

I heard about this approach some time ago, but haven't seen any data
sheets yet.  But static column mode?  I suppose that would imply these
guys actually latch the internal row address on a CS* like input, 
but allow the internal column address to be statically varied.  But
if normal access time is 35ns, what's static column likely to be?

>--Steve


-- 
Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
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