Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!usc!zaphod.mps.ohio-state.edu!uakari!xanth!mcnc!thorin!unc!mccabe
From: mccabe@unc.cs.unc.edu (Dan McCabe)
Newsgroups: comp.sys.transputer
Subject: Semantics of In and Out instructions for memory channels?
Message-ID: <12243@thorin.cs.unc.edu>
Date: 25 Feb 90 21:38:04 GMT
Sender: news@thorin.cs.unc.edu
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Does anyone out in Netland know details about the semantics of the In and Out
instructions when a memory channel is specified?  I have examined the
transputer compiler writers' guide (tcwg), but unfortunately it is rather vague
on this matter.  Also the article by Nicoud and Tyrrell in the 6/89 issue
of IEEE Micro provides no details about these instructions (although
they do provide some details of the alt and par instructions on which tcwg
is equally vague).

I know that a channel is initialized with NotProcess.p (-1).  I presume
that a process descriptor is kept in the channel variable.  Is the
channel a linked list of waiting processes?  It seems to me that this would
have to be the case, since several processes may Out to the same channel before
another process does an In.  Are the registers saved in the workspace if
the instruction blocks (when Out executes and there is no pending In or
vice versa)?  If you treat the list of processes as a queue, you also need
a tail ptr for efficient insertion (as is the case for general process
scheduling).  Is there some encoding that says that the channel is waiting
either for an In instruction or for and Out instruction?

Would anyone care to discuss some of these details, either publicly via news
or privately via mail?  If you have pointers to additional references, those
would also be appreciated.

Thanx in advance,
danm