Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!usc!ucsd!ucbvax!hplabs!hpfcso!hpfcdc!lois
From: lois@hpfcdc.HP.COM (Lois Gerber)
Newsgroups: comp.unix.questions
Subject: Re: The intimate details of 'make'
Message-ID: <5740048@hpfcdc.HP.COM>
Date: 22 Feb 90 23:43:59 GMT
References: <2253@rex.cs.tulane.edu>
Organization: HP Ft. Collins, Co.
Lines: 32

A good readable reference for using make is "Managing Project with Make",
A Nutshell handbook, by Steve Talbott, published by O'Reilly & Associates,
Inc. ISBN 0-937175-18-8.  It is out of print but you can still get
copies;  I know because I just got one a few weeks ago.

From the description of your problem, I am not sure what you are
trying to do, but I can tell you a few things which may point
you in the right direction.

1) Make reads the environment in which it is executed and uses all
   variable declarations in environ() as macros for itself.  If
   this variable is not redeclared in the makefile as something else,
   the environment value will be used.  i.e. if CCOPTS is defined
    in the environment and not in the makefile, any reference to
    $(CCOPTS) in the makefile will use the value set in the environment.

2) Some makes have an include feature.  If you have a line in the
   makefile of the form:

include filename

   make will read that file as another makefile and include all
   macro definitions and rules in it as part of its environment.
   In this way, you can centralize common definitions in one file
   and just include that file in a multitude of other files, 
   preventing your need to repeat define things.

I might be able to help more if I had a clearer understanding of
exactly what you are trying to accomplish.

Lois Gerber
HP, Fort Collins