Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!milano!peyote!woan
From: woan@peyote.cactus.org (Ronald S. Woan)
Newsgroups: comp.arch
Subject: Re: IBM RISC
Summary: what??!!
Keywords: what integer parallelism?
Message-ID: <438@peyote.cactus.org>
Date: 28 Feb 90 06:13:40 GMT
References: <8064@pt.cs.cmu.edu> <7454@pdn.paradyne.com> <1653@awdprime.UUCP> <32344@shemp.CS.UCLA.EDU>
Organization: Capital Area Central Texas Unix Society, Austin, TX
Lines: 20

In article <32344@shemp.CS.UCLA.EDU>, frazier@oahu.cs.ucla.edu (Greg Frazier) writes:
> My understanding is that there are 3 ALU's, each with it's own
> pipeline, and that is where the 5 ops/cycle peak is (i.e. 3 int
> ops, 1 fp mult and 1 fp add).  Of course, you don't often get
> more than 1 int opn at a time, as is revealed by the discrepancy
> between the fp and int benchmarks.

Where did this come from? From the simulator and talking to the designers,
the three ALUs are the float add, float mult, and integer op units. If we
could do (and schedule) multiple integer ops/cycle, you would be seeing
some even more phenomenal benchmark results. I repeat 5 op/peak achieved
by two branch instructions (counting these as integer ops these days?),
float add-multiply instruction, and a single integer op.

						Ron
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