Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!mit-eddie!uw-beaver!uw-june!kolding
From: kolding@cs.washington.edu (Eric Koldinger)
Newsgroups: comp.arch
Subject: Re: IBM RISC System/6000  AS/400
Message-ID: <10893@june.cs.washington.edu>
Date: 28 Feb 90 07:06:40 GMT
References: <8009@pt.cs.cmu.edu> <36083@mips.mips.COM> <43003@ames.arc.nasa.gov> <00932ED5.34B5AE20@KING.ENG.UMD.EDU> <20714@cfctech.cfc.com>
Reply-To: kolding@june.cs.washington.edu (Eric Koldinger)
Organization: University of Washington, Computer Science, Seattle
Lines: 19

In article <20714@cfctech.cfc.com> joel@cfctech.cfc.com (Joel Lessenberry) writes:
>
>        During the announcement, and several times after, IBM has 
>        pointed out that the processor in the low end AS/400 
>        systems is different than the processor in the rack mount
>        systems...in fact that low end systems is RISC based.
>
>        Could this RISC be similar to the System/6000?

No.  In fact, if I remember correctly, all of the various AS/400 models have
microcode (what IBM calls HMC, or horizontal microcode), so none of them would
qualify as RISC based at any level.  They also all have substantial OS support,
called VMC, or vertical microcode.

-- 
        _   /|                          Eric Koldinger
        \`o_O'                          University of Washington
          ( )     "Gag Ack Barf"        Department of Computer Science
           U                            kolding@cs.washington.edu