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From: touati@ucbarpa.Berkeley.EDU (Herve J. Touati)
Newsgroups: comp.arch
Subject: Re: IBM RISC
Keywords: what integer parallelism?
Message-ID: <34586@ucbvax.BERKELEY.EDU>
Date: 28 Feb 90 16:03:37 GMT
References: <8064@pt.cs.cmu.edu> <7454@pdn.paradyne.com> <1653@awdprime.UUCP> <32344@shemp.CS.UCLA.EDU> <438@peyote.cactus.org>
Sender: usenet@ucbvax.BERKELEY.EDU
Reply-To: touati@ucbarpa.Berkeley.EDU.UUCP (Herve J. Touati)
Organization: University of California, Berkeley
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In article <438@peyote.cactus.org> woan@peyote.cactus.org (Ronald S. Woan) writes:
[...]
>Where did this come from? From the simulator and talking to the designers,
>the three ALUs are the float add, float mult, and integer op units. If we
>could do (and schedule) multiple integer ops/cycle, you would be seeing
>some even more phenomenal benchmark results. I repeat 5 op/peak achieved
>by two branch instructions (counting these as integer ops these days?),
>float add-multiply instruction, and a single integer op.
>
>						Ron
>-- 
>+-----All Views Expressed Are My Own And Are Not Necessarily Shared By------+
>+------------------------------My Employer----------------------------------+
>+ Ronald S. Woan         @cs.utexas.edu:romp!auschs!woan.austin.ibm.com!ron +
>+ second choice:                                     woan@peyote.cactus.org +

My understanding (after an IBM presentation here) is that the two
branch instructions that can be executed in one cycle have to be
understood of the branch unit. Only one can actually be a branch. The
second is a condition code operation. One of the innovations of R/6000
architecture is that the processor comes with several (8) condition
code registers. There are bits in the opcodes of instructions that can
set the condition codes to specify in which register the condition
code should be put. The processor provides boolean operations on the
condition code registers as separate instructions, and only those
instructions can be executed in parallel with a branch by the branch
unit. 

--- Herve' Touati
UC Berkeley