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From: oscar@oscar.uucp (Oscar R. Mitchell;3A-17 (045))
Newsgroups: comp.arch
Subject: Re: IBM RISC
Keywords: what integer parallelism? multiops five
Message-ID: <2778@auschs.ibm.com>
Date: 28 Feb 90 17:09:54 GMT
References: <8064@pt.cs.cmu.edu> <7454@pdn.paradyne.com> <1653@awdprime.UUCP> <1666@awdprime.UUCP> <32344@shemp.CS.UCLA.EDU>
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Summary:Clarification of the 5 ops/cycle comments !!!!
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In article <32344@shemp.CS.UCLA.EDU> frazier@oahu.UUCP (Greg Frazier) writes:
>In article <1666@awdprime.UUCP> @cs.utexas.edu:ibmchs!auschs!woan.austin.ibm.com!ron writes:
>>
>>In article <1653@awdprime.UUCP>, ron@woan.austin.ibm.com (Ronald S.
>>Woan/2100000) writes:
>+|> I must have missed something here... What integer unit parallelism?
>+|> From what I understand, the integer unit is a single pipeline (5?
>+|> stages), so it can never do better than one instruction/cycle. To get
>+|> five/cycle, you need two branches, float add, float mult, and integer
>+|> operation. Only an amazing compiler can schedule an application to use
>+|> this frequently.
>+
>+Some people within IBM have asked me to clarify my statements (I
>[stuff deleted]
>+branches with respect to integer operations; however, with a single
>+integer operation pipeline, you will never see more than one integer
>+operation/cycle. Also, it would take an amazing compiler to schedule
>+five concurrent operations regularly for any imaginable typical
>+application to maintain the peak execution figure that some people
>+have been quoting.
>
>My understanding is that there are 3 ALU's, each with it's own
>pipeline, and that is where the 5 ops/cycle peak is (i.e. 3 int
>ops, 1 fp mult and 1 fp add).  Of course, you don't often get
>more than 1 int opn at a time, as is revealed by the discrepancy
>between the fp and int benchmarks.
>
>+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+=+
>Greg Frazier                           "Big A, little a / What begins with A?
>frazier@CS.UCLA.EDU                    Aunt Annie's Alligator / A ... a ... A"
>!{ucbvax,rutgers}!ucla-cs!frazier                      _Dr._Seuss's_ABCs_



I hope the following will clarify any confusion about the
comments made about the RISC System/6000's five (5) operations/second:

	The RS/6000 is composed of several "Sub-Units"
	some of these are:
	        Instruction Cache Unit   (ICU)
	        Fixed Point Unit         (FXU)
	        Floating Point Unit      (FPU)
	        Data Cache Unit          (DCU)

Therefore, in order for the RS/6000 to accomplish 5 operations/cycle
the:
       ICU would be executing a Branch/IFetch and a Condition
       Register operation.

       FXU would be executing a Interger operation.

       FPU would be executing the Multiply-Add/Sub Instruction
	 (Note: This instruction is done with only a SINGLE rounding
	        operation - this is not a multiply {w/rounding}
	        followed by an addition/subtraction {w/rounding} )


Regards,
Oscar.
><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><
 IBM Advanced Workstations Division                  IBM Tieline:  678-6733
 RISC System/6000(tm) Floating Point Processor Design Group
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#include <standard.disclaimer>  /* I DO NOT speak for IBM */  Oscar R. Mitchell