Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!samsung!uunet!convex!patrick
From: patrick@convex.com (Patrick F. McGehearty)
Newsgroups: comp.arch
Subject: Re: Cache Size
Keywords: locality of reference, cache size
Message-ID: <100324@convex.convex.com>
Date: 28 Feb 90 17:37:05 GMT
References: <7393@pdn.paradyne.com> <76700146@p.cs.uiuc.edu> <1990Feb26.022057.28461@Neon.Stanford.EDU> <8189@pt.cs.cmu.edu> <8848@boring.cwi.nl>
Sender: news@convex.com
Organization: Convex Computer Corporation; Richardson, TX
Lines: 11

In article <8848@boring.cwi.nl> dik@cwi.nl (Dik T. Winter) writes:
>In article <8189@pt.cs.cmu.edu> koopman@a.gp.cs.cmu.edu (Philip Koopman) writes:
>1.  No vector registers, bypass cache (Cyber 995).
>2.  Vector registers, bypass cache (i know none).
>3.  No vector registers, through cache (again, i know none).
>4.  Vector registers, through cache (IBM 3090, Convex, Alliant, Gould).

Actually, in the Convex C2 series, vector loads and stores bypass the cache.
Scalar operations use the cache.  One argument for this design is that
the large amount of data used in vector operations would quickly invalidate
most scalar data in the cache, such as local variables, loop limits, etc.