Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!uunet!jarthur!elroy.jpl.nasa.gov!decwrl!sgi!rpw3@rigden.wpd.sgi.com
From: rpw3@rigden.wpd.sgi.com (Rob Warnock)
Newsgroups: comp.arch
Subject: Re: Info on Barrel Processors wanted
Message-ID: <52305@sgi.sgi.com>
Date: 1 Mar 90 07:01:31 GMT
References: <1990Feb23.193659.565@Stardent.COM> <38965@apple.Apple.COM> <1990Feb28.170243.1745@mks.com>
Sender: rpw3@rigden.wpd.sgi.com
Reply-To: rpw3@rigden.UUCP (Robert P. Warnock)
Organization: Silicon Graphics, Inc., Mountain View, CA
Lines: 29

In article <1990Feb28.170243.1745@mks.com> chrisp@mks.com
(Chris Phillips) writes:
+---------------
| In article <38965@apple.Apple.COM> baum@apple.UUCP (Allen Baum) writes:
| >>In article <1990Feb23.193659.565@Stardent.COM> sporer@stardent.UUCP writes:
| >>I am looking for references to literature on Barrel Processors. I have seen
| >>the original articles on the CDC6600 Peripheral Processors. 
| >Similar concepts were used in the Denelcor HEP and the upcoming TERA Horizon.
| And also in the console and iop of the Amdahl 580, 58xx and (I think) 59xx.
| Barrel processors were also used in several Hitachi/NAS machines. And most of
| the more recent Cyber 170 and Cyber 180 machines... except the Cyber 930
+---------------

Don't forget that the inverse concept, in a nearly degenerate form, was used
in a lot in embedded controllers with 8-bit CPUs of the 6800 or 6809 families
(and maybe the 6502 as well?). Said micros had memory cycles which really
used the bus only during the second half of the clock cycle (though the
address would come out late in the first half). As a result, by using memory
twice as fast as normal, and by running two micros on opposite clock phases,
you could get a "2-CPU multiprocessor" for not much more than the cost of one.

-Rob


-----
Rob Warnock, MS-9U/510		rpw3@sgi.com		rpw3@pei.com
Silicon Graphics, Inc.		(415)335-1673		Protocol Engines, Inc.
2011 N. Shoreline Blvd.
Mountain View, CA  94039-7311