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From: lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay)
Newsgroups: comp.arch
Subject: Signetics VLIW
Message-ID: <8241@pt.cs.cmu.edu>
Date: 1 Mar 90 19:26:42 GMT
Organization: Carnegie-Mellon University, CS/RI
Lines: 15

Philips/Signetics has now officially revealed its VLIW chip.
So far, I've heard:

	2 integer ALUs
	32 bit path to memory
	6 ops/clock
		- 2 integer
		- 1 branch
		- 1 "constant generator" ??
		- 1 memory operation
		- ?that leaves one op unaccounted for?

Pretty scanty. Surely, someone out there has details?
-- 
Don		D.C.Lindsay 	Carnegie Mellon Computer Science