Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!uwm.edu!rutgers!netnews.upenn.edu!grad2.cis.upenn.edu!iyengar From: iyengar@grad2.cis.upenn.edu (Anand Iyengar) Newsgroups: comp.arch Subject: Re: 64-bit addresses Message-ID: <20534@netnews.upenn.edu> Date: 18 Feb 90 04:21:44 GMT References: <9708@spool.cs.wisc.edu> <20270@cfctech.cfc.com> <11112@encore.Encore.COM> <753@dgis.dtic.dla.mil> <3606@uceng.UC.EDU> <757@dgis.dtic.dla.mil> <4852@scolex.sco.COM> <29718@brunix.UUCP> Sender: news@netnews.upenn.edu Reply-To: iyengar@grad2.cis.upenn.edu.UUCP (Anand Iyengar) Organization: The Lab Rats Lines: 22 In article <29718@brunix.UUCP> phg@cs.brown.edu (Peter H. Golde) writes: >One might note that implementing a 64-bit address space >with 64 KB pages and 8 bytes/page in the page table requires >2 billion megabytes of page-table space. Hmmmmm..... This is for the final level of the translation, and it need not be fully resident (!). With each successive (K step) indirection you'd add 2^(64 - 13*k) { 1 <= K <= 4 } bytes in page tables. Only the highest level (lowest K) need be loaded. However, you do buy the space with time (successive look-ups). What's the general feeling on future page sizes (I'm guessing that 64K was picked here to make the page-tables smaller)? Is it reasonable to assume that they are going to increase also (as bandwidth/latency increases), or will we lose more by making pages larger? Anand. -- "Surely you're not happy, you no longer play the game..." {inter | bit}net: iyengar@eniac.seas.upenn.edu uucp: !$ | uunet --- Lbh guvax znlor vg'yy ybbx orggre ebg-guvegrrarg? ---