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From: alan@oz.nm.paradyne.com (Alan Lovejoy)
Newsgroups: comp.arch
Subject: Re: Prefetch instruction (was Re: BitBlt, new instructions for RISC.)
Message-ID: <7499@pdn.paradyne.com>
Date: 2 Mar 90 06:06:01 GMT
References: <7466@pdn.paradyne.com> <BBC.90Feb25195510@legia.rice.edu> <7488@pdn.paradyne.com> <203@zds-ux.UUCP>
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Reply-To: alan@oz.paradyne.com (Alan Lovejoy)
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Organization: AT&T Paradyne, Largo, Florida
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In article <203@zds-ux.UUCP> gerry@zds-ux.UUCP (Gerry Gleason) writes:
<Let me see if I understand this correctly.  For it to help to put the load
<early, the instruction pipeline would have to be able to continue executing
<as long as no instruction references the loaded register (this is what the
<scoreboard does, indicates which registers are "valid").  Is this a correct
<interpretation of what you said?

Yes.  That's the main point of having a scoreboard, after all.

Notice how the relative importance of things depends on the environment as
a whole, as well as the tasks you wish to accomplish?! "It is impossible to
do just one thing."

____"Congress shall have the power to prohibit speech offensive to Congress"____
Alan Lovejoy; alan@pdn; 813-530-2211; AT&T Paradyne: 8550 Ulmerton, Largo, FL.
Disclaimer: I do not speak for AT&T Paradyne.  They do not speak for me. 
Mottos:  << Many are cold, but few are frozen. >>     << Frigido, ergo sum. >>