Path: utzoo!mnetor!tmsoft!torsqnt!jarvis.csri.toronto.edu!cs.utexas.edu!usc!snorkelwacker!mit-eddie!uw-beaver!uw-june!dgb
From: dgb@cs.washington.edu (David Bradlee)
Newsgroups: comp.arch
Subject: more on i860 mulitply
Message-ID: <10941@june.cs.washington.edu>
Date: 3 Mar 90 19:07:00 GMT
Organization: U of Washington, Computer Science, Seattle
Lines: 46

A couple of additional thoughts on the i860 floating point
multiplier.  I think we're clear on the fact that
double multiplies use each stage for 2 cycles.  So, using the pipelined
instructions a multiply would look like:
f8 = f4 * f6;

cycle
0	pfmul.dd f4,f6,f0
1
2	pfmul.dd f0,f0,f0
3
4	pfmul.dd f0,f0,f8


As far as the single/double and vice versa multiply transitions, looking at
it in the light of the double mult taking 2 cycles per stage makes it
a little clearer.

Let Di = double multiply, Si = single multiply

cycle	0  1  2  3  4  5  6  7  8  9  10 11
stage	-----------------------------------
  1	D1 D1 D2 D2 S1 S2 S3 D3 D3 D4 D4
  2	      D1 D1    S1 S2 S3    D3 D3
  3	            0     S1
	-----------------------------------
result	            D1 0  a  S1    b     D3
	   ^     ^              ^     ^
	   |     |              |     |
	   no instrs issued on these 4 cycles

There is no way to obtain a result from the mult pipeline.  Hence the
only questions are whether 'a' or 'b' are meaningful values.  I would
say that 'a' cannot be since D2 would need stage 2 for 2 cycles,
putting it in conflict with S1.  I would also say that 'b' cannot,
since the double mult would store the result of the stage 2.  However,
the book says, "The second previous operation is discarded (S2).  The
next pipelined multiplier operation stores the single-precision
result."  That would mean 'b' = S3.  This seems strange, but sometimes
truth is stranger than fiction.

	Dave Bradlee
	Department of Computer Science and Engineering, FR-35
	University of Washington
	Seattle, WA  98195
	dgb@cs.washington.edu