Path: utzoo!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!uunet!csinc!rpeglar
From: rpeglar@csinc.UUCP (Rob Peglar)
Newsgroups: comp.arch
Subject: Re: 64-bit addresses
Summary: Page sizes?
Message-ID: <172@csinc.UUCP>
Date: 2 Mar 90 18:58:41 GMT
References: <9708@spool.cs.wisc.edu> <20270@cfctech.cfc.com> <20534@netnews.upenn.edu>
Organization: Control Systems, Inc., St. Paul MN
Lines: 25

In article <20534@netnews.upenn.edu>, iyengar@grad2.cis.upenn.edu (Anand Iyengar) writes:
(some deletions)

> 
> 	What's the general feeling on future page sizes (I'm guessing that
> 64K was picked here to make the page-tables smaller)?  Is it reasonable
> to assume that they are going to increase also (as bandwidth/latency
> increases), or will we lose more by making pages larger?  

Well, if the current "trend" of incorporating mainframe/supercomputer-ish
architecture concepts (e.g. superscalar) continues, history has given us
page sizes as large as 512KB (Cyber 205) and even 2MB (ETA-10, although
the OS'es never actually supported it).  

The VAT mechanism in these machines was slightly different, in that the
205 had a global page table and the 10 used local (one per task) page
tables.  The seemingly large page sizes solved both the page table
size issue and the long vector ops without faulting issue.

Rob
-- 
Rob Peglar	Control Systems, Inc.	2675 Patton Rd., St. Paul MN 55113
...uunet!csinc!rpeglar		612-631-7800

The posting above does not necessarily represent the policies of my employer.