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From: mhorne@ka7axd.WV.TEK.COM (Michael T. Horne)
Newsgroups: comp.dsp,tek.dsp
Subject: 56K read-modify-write cycle question
Message-ID: <6333@orca.wv.tek.com>
Date: 5 Mar 90 04:23:21 GMT
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Organization: Visual Systems Group, Tektronix, Inc., Wilsonville, OR
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I've run across a problem that I haven't been able to resolve yet.  So far
Motorola hasn't been of much help (yet).

When using the 56K read-modify-write (RMW) instructions (i.e. BCHG, BCLR and
BSET), the 56K Advance Information Data Sheet states that the address bus,
DS, PS, and X/Y strobes do not change state, thereby providing an indivisible
bus cycle for setting/clearing semaphores, etc.  However, I see no information
regarding RMW bus operation when using the Bus Strobe/Wait (BS/WT) feature
of the 56K.

Am I correct in assuming that the address lines and associated strobes will
remain in the same state during the entire RMW cycle, with only BS changing
state at the beginning/end of the read and write sub-cycles?  Is it safe to
assume that if DS or PS are asserted that a valid bus cycle is underway, even
if BS is currently not asserted, as in the case of RMW between the read and
write operations?

This is truly a subtle point, but I haven't found any bus timing diagrams for
this case (the bus timing diagrams for BS/WT operation are sketchy at best),
and I'd like to know how the bus operates for this transaction.

Thanks in advance for any info/pointers!

Mike