Path: utzoo!censor!geac!torsqnt!jarvis.csri.toronto.edu!rutgers!usc!snorkelwacker!bloom-beacon!bu.edu!buengc!bph
From: bph@buengc.BU.EDU (Blair P. Houghton)
Newsgroups: comp.lsi
Subject: Re: A Question On Biasing Circuits
Message-ID: <5450@buengc.BU.EDU>
Date: 4 Mar 90 20:04:02 GMT
References: <4025@mit-caf.MIT.EDU>
Reply-To: bph@buengc.bu.edu (Blair P. Houghton)
Followup-To: comp.lsi
Organization: Boston Univ. Col. of Eng.
Lines: 45

In article <4025@mit-caf.MIT.EDU> shers@mit-caf.UUCP
(Alexander The Great Sherstinsky) writes:
>Vi   C
>----||----*-- Vo
>          |
>          /
>          \ R
>          /
>          \
>          |
>          GND
[...and asks how to bias this highpass so that Vo is about Supply/2...]

That's the AC model.  The DC model can look like:

          Vdd
          |
          /
          \ 2R
          /
          \
Vi   C    |
----||----*-- Vo  (Now Vo == Vdd/2)
          |
          /
          \ 2R
          /
          \
          |
          GND

Which is the answer.

There's a problem if you use turned-off enhancement FET's
for the 2R values, in that process control is very spotty
(and of limited economic value) in CMOS, and the pullup's
off-impedance may be an order of magnitude different from
the pulldown's, and good luck predicting which way.

Now, if you've got an _analog_ CMOS line on which to
produce these chips, or a process engineer who doesn't
mind a few days of knob-twiddling...

				--Blair
				  "Them's the breaks."