Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!usc!snorkelwacker!mit-eddie!mit-amt!mit-caf!shers From: shers@mit-caf.MIT.EDU (Alexander The Great Sherstinsky) Newsgroups: comp.lsi Subject: Re: A Question On Biasing Circuits Message-ID: <4029@mit-caf.MIT.EDU> Date: 4 Mar 90 20:37:26 GMT References: <4025@mit-caf.MIT.EDU> <5450@buengc.BU.EDU> Reply-To: shers@mit-caf.UUCP (Alexander The Great Sherstinsky) Organization: Microsystems Technology Laboratories, MIT Lines: 57 In article <5450@buengc.BU.EDU> bph@buengc.bu.edu (Blair P. Houghton) writes: #In article <4025@mit-caf.MIT.EDU> shers@mit-caf.UUCP #(Alexander The Great Sherstinsky) writes: #>Vi C #>----||----*-- Vo #> | #> / #> \ R #> / #> \ #> | #> GND #[...and asks how to bias this highpass so that Vo is about Supply/2...] # #That's the AC model. The DC model can look like: # # Vdd # | # / # \ 2R # / # \ #Vi C | #----||----*-- Vo (Now Vo == Vdd/2) # | # / # \ 2R # / # \ # | # GND # #Which is the answer. # #There's a problem if you use turned-off enhancement FET's #for the 2R values, in that process control is very spotty #(and of limited economic value) in CMOS, and the pullup's #off-impedance may be an order of magnitude different from #the pulldown's, and good luck predicting which way. # #Now, if you've got an _analog_ CMOS line on which to #produce these chips, or a process engineer who doesn't #mind a few days of knob-twiddling... # # --Blair # "Them's the breaks." Thanks. But this is what my main question is: How to achieve the biasing point reliably at the mid point (or nearby) between the supply rails and get a huge equivalent resistance (1Gohm) would be very nice. Alex -- +-------------------------------+------+-----------------+---------------------+ |Alexander The Great Sherstinsky|me |shers@caf.mit.edu|To become as refined | |Alexander Semyon Sherstinsky |myself|shers@caf.mit.edu|a person as possible.| |Alex Sherstinsky |I |shers@caf.mit.edu|*********************|