Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!yale!mintaka!mit-eddie!mit-amt!mit-caf!shers
From: shers@mit-caf.MIT.EDU (Alexander The Great                                                                     Sherstinsky)
Newsgroups: comp.lsi
Subject: Again, about my RC network question.
Message-ID: <4032@mit-caf.MIT.EDU>
Date: 5 Mar 90 02:16:06 GMT
Reply-To: shers@mit-caf.UUCP (Alexander The Great                                                                     Sherstinsky)
Organization: Microsystems Technology Laboratories, MIT
Lines: 23

About the question I posted earlier regarding an RC highpass filter.
It is going to be designed in 2um 2poly 2metal MOSIS Scalable CMOS process.
All I am trying to do is make R as big as possible to lower the break
frequency, since C is fixed at 1pF.  Also, the dc bias has to be definite,
because it is important to have the output signal stay between the rails.

So, to sum up:

It is an IC circuit.
Power and pin limitations are to be ignored.
It's not a high performance circuit, but to have that bias point in mid-rail
and high resistance (~1 Mohm would be nice) is important.

It is a non-supported project, so I feel no problems asking for outside
help.

Thanks for reading,
Alex
-- 
+-------------------------------+------+-----------------+---------------------+
|Alexander The Great Sherstinsky|me    |shers@caf.mit.edu|To become as refined |
|Alexander Semyon Sherstinsky   |myself|shers@caf.mit.edu|a person as possible.|
|Alex Sherstinsky               |I     |shers@caf.mit.edu|*********************|