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From: shers@mit-caf.MIT.EDU (Alexander The Great                                                                     Sherstinsky)
Newsgroups: comp.lsi
Subject: Re: A Question On Biasing Circuits
Message-ID: <4033@mit-caf.MIT.EDU>
Date: 5 Mar 90 05:07:54 GMT
References: <4025@mit-caf.MIT.EDU> <12205@venera.isi.edu>
Reply-To: shers@mit-caf.UUCP (Alexander The Great                                                                     Sherstinsky)
Organization: Microsystems Technology Laboratories, MIT
Lines: 64

In article <12205@venera.isi.edu> tornheim@venera.isi.edu.UUCP (David Tornheim) writes:
#In article <4025@mit-caf.MIT.EDU> shers@mit-caf.UUCP  writes:
#>Vi   C
#>----||----*-- Vo
#>          |
#>          /
#>          \ R
#>          /
#>          \
#>          |
#>          GND
#>         
#>I need help in finding the right circuit for my thesis.  Basically,
#>I am designing a highpass RC filter whose break point frequency is as
#>small as I can get.  C is fixed at 1pF, so the objective is to make R big.
#>Thus, what I need is a biasing network that will keep the node Vo 
#>at 2.5 V DC, while making the R huge.  The supply voltages are 0 V and 5 V,
#>which is why I want an approximately 2.5 V DC level.  It looks like what
#>I want is a voltage source with a huge source impedance (1 Gohm would 
#>be nice).  It doesn't have to be linear, the whole circuit doesn't have
#>to be linear.
#
#Another person replied with a configuration using a large resistor connected
#to Vdd and another to Vss.  This, however, is not necessary.  Instead
#one could connect a large resistor to a 2.5V voltage source (which has
#a relatively low Thevenin resistance for the problem).  Creating a 2.5V voltage
#source can be done using a voltage divider with resistors or
#transistors (Gregorian & Temes p. 127).  Creating the large series
#resistance to the 2.5V source is again the hard part.  I simulated
#a few configurations below with two transistors (one of which will
#be in the subthreshold region).  These are similar to using two
#back to back diodes.  The simulations gave promising results.
#Note:  The models used are from MOSIS and we do not measure
#subthreshold currents nor try to model them.
#The BSIM model and LEVEL=2 models gave answers different by an order
#of magnitude.
#
#Two other thought:
#1) Use a MOSFET with drain connected to 2.5V and source connected to
#   your output.  Then connect the gate to a very high frequency clock
#   with a very low duty cycle.  (Variations on this theme are of
#   course possible using two devices, one connected to Vdd and the
#   other to Vss).
#2) Use an amplifier with very high output impedance, connected so
#   that it acts as a resistor.
#
#-David Tornheim
#

Thanks for your response.  As you said, biasing mosfets in subthreshold
region is unreliable.  I have already tried all the configurations you
propose.  Whenever you get an acceptable resistance, you have no
certainty in whether or not your bias point will be at 2.5 V.  Also,
neither a separate 2.5 V rail nor that "super fast" clock are available.
The approach using an opamp seems to be too costly, but I haven't really
given it enough thought.

Thanks for all further help,
Alex
-- 
+-------------------------------+------+-----------------+---------------------+
|Alexander The Great Sherstinsky|me    |shers@caf.mit.edu|To become as refined |
|Alexander Semyon Sherstinsky   |myself|shers@caf.mit.edu|a person as possible.|
|Alex Sherstinsky               |I     |shers@caf.mit.edu|*********************|