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From: hue@netcom.UUCP (Jonathan Hue)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: One more Amiga RAM question. ;*)
Message-ID: <8068@netcom.UUCP>
Date: 28 Feb 90 08:59:09 GMT
References: <928@orange9.qtp.ufl.edu>
Distribution: na
Organization: NetCom- The Bay Area's Public Access Unix System {408 249-0290 guest}
Lines: 56

In article <928@orange9.qtp.ufl.edu> sutherla@qtp.ufl.edu (scott sutherland) writes:
>	How can the A2091, which uses 16-bit RAM, and the A2630, which
>uses 32-bit RAM, use the same type of chips, with the only difference
>being the SPEED??????????  If this is true, do I use the same number
>of the faster chips for 2 Megs on the A2630?? 

The DRAM is 256Kx4 bits, not 16 or 32.  Instead of needing 4 chips to provide
a 16-bit wide path to memory, you need 8 chips for a 32-bit wide path.
2MB of either is the same number of chips, but the A2630 takes ZIPs and
the 2091 takes DIPs

>	The specs on the A2630 state that it comes with 2 Megs of 
>100 ns RAM.  According to the Amiga World review (March 1990), they
>should have used 80 ns or 70 ns RAM, like the Hurricane and other
>'030 boards.  AW also says that the 2 Megs on the A2630 are soldered
>in and would be difficult to remove.  My question is this.  If I leave
>the 2 Megs of 100 ns RAM in there and decide to add two more Megs of
>32-bit RAM, DO I HAVE TO USE 100 ns RAM, OR CAN I USE 70 OR 80 ns RAM
>TO IMPROVE PERFORMANCE????   What will be the effect, if any, (especially
>adverse effects) of having 2 different speeds of RAM on the board?  Would
>I be better off removing the original 2 Megs and using the same chips for
>all 4 Megs?

How kind of the writers at AW to share their infinite wisdom with us.
80ns DRAM is going to be close to the edge of being able to drop a wait
state (Dave, help).  I'm pretty sure 70ns is fast enough to drop a wait
state, but I haven't seen 70ns access time DRAM advertised in any of the
local microcomputer rags.

When performing an asynchronous bus transfer, the '030 waits for a comple
signals called /DSACK0 and /DSACK1 to tell it when data is valid and it
can grab it off the bus.  DRAMs don't have pins that generate these signals,
you either roll your own DRAM controller out of PLDs or buy one off the
shelf to generate these signals.  The system designer decides something like:
"Hey, 100ns or faster DRAM is available cheap, so I'll have my PALs
generate /DSACK[01] XX ns after /DS and tell the user to use 100ns or faster
DRAM to populate this thing."

So if you put in 70ns DRAM, the CPU still waits until it sees /DSACK[01]
until it grabs the data.  There isn't a way for it to know how fast the
memory is.  Now, I may be dreaming, but I swear I've seen the data sheet
for a *programmable* Samsung DRAM controller which could do all sorts of
fancy stuff, like generate /DTACK faster of slower for different chunks of
memory (address ranges), generate nibble and page mode cycles, etc.  If I
wasn't dreaming, this thing could be programmed to generate /DTACK faster if
you had a chunk of faster memory.


>What in the world is a ZIP package???  Again, none of the advertisers in CS 
>mention anything about ZIP!!  They mentions SIMMS, but NO ZIPS.  Why do I need
>ZIP?  How do I determine if a chip advertised in CS is ZIP or not???

ZIP is zigzag.  Good luck finding these cheap, let us all know if you find
a source.

-Jonathan