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From: stephen@hpdmd48.HP.COM (Stephen Holmstead)
Newsgroups: comp.sys.amiga.hardware
Subject: DRAM expansion hardware (long)
Message-ID: <19770001@hpdmd48.HP.COM>
Date: 28 Feb 90 22:34:48 GMT
Organization: Hewlett Packard - Boise, ID
Lines: 73

Ok, hardware experts.  I built a DRAM memory expansion board that seems to
work for me:  I wrote a 'C' program that can read and write to all locations.
I have tried different patterns, etc.  It works.  OK.

I have not put on any autoconfig hardware, so I try to add this memory to
the system free memory list with ADDMEM and ADDMEM dies stating 'Couldn't
clear memory.  Memory location bad.'  What?  I can read and write just fine.
What's wrong?  What does ADDMEM do that I don't?  Here is an output of the
key signals during a read access (I also have them for the writes, if
desired).  Is there any major faults in this picture?  What are the pitfalls
that I should look for?

CDAC  |-------_______-------_______-------_______-------_______-------_______|
_AS   |-------------___________________________________----------------------|
R_W   |----------------------------------------------------------------------|
_RAS  |---------------__________________________________---------------------|
_CAS  |--------------------______________________________--------------------|
_UDS  |-------------___________________________________----------------------|
_LDS  |-------------___________________________________----------------------|
_OVR  |-------------__________-----------------------------------------------|
_DTACK|-----------------------__________________________---------------------|
D0-15 |++++++++++++++++++++++++=======================================+++++++|
CDAC  |-------_______-------_______-------_______-------_______-------_______|

NOTE: each character is 10 ns wide.

KEY: ---  High signal
	 ___  Low signal
	 +++  High impedence state
	 ===  valid (High or Low) signal
	 
SIGNALS:

CDAC   - 7M clock signal (pin  15)
_AS    - Address strobe (pin 74)
R_W    - Read/Write (pin 68)
_RAS   - Row address strobe (not on expansion bus)
_CAS   - Column address strobe (not on expansion bus)
_UDS   - Upper data strobe (pin 72)
_LDS   - Lower data strobe (pin 68)
_OVR   - Override strobe (pin 17)
_DTACK - Data transfer acknowledge (pin 66)
D0-15  - Data lines

I have a couple of other questions:  Since the 7M clock that feeds the
MC68000 is not available on the bus, I am using the CDAC.  Is this ok?
I think I have seen a couple of time when this clock appeared to glitch.
Is this true?  On the schematics for the A500, the CDAC appears to get
inverted before it gets to the expansion bus.  Does this put it 90 degrees
out of phase with the 7M clock?  Or is it already out of phase?  Is this
a good clock signal?

Also, since the "GARY" chip automagically generates the _DTACK signal for
the MC68000, I am using the _OVR signal on the expansion bus (that feeds
into "GARY") to keep the _DTACK from falling before my data is ready.  Is
this the "correct" thing to do?  I noticed that there is also a _OVL signal.
What is that for?

Since the data latches on the falling edge of the clock following the first
falling edge of the clock that latches the fall of _DTACK, doesn't the UDS
and LDS still have to be valid at this point.  According the the CDAC, the
UDS and LDS rise about 20 ns BEFORE the data is latched.

Are there any common hints that I can try to get this thing to work with an
Amiga?

Thanks for your patience in reading through this.  Remember, I'm a CS weenie,
not an EE weenie.

 ____       ____
|   / /_  __\   | Disk      0S/2 == 1/2 OS (Leo Schwab)      Stephen Holmstead
|  | / / /_/ |  | Mechanism          //             ...!hplabs!hpdmlge!stephen
|___\   /   /___| Division         \X/ Amiga        stephen@hpdmlge.boi.hp.com