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From: rcomr@koel.co.rmit.oz (Mark Rawling)
Newsgroups: comp.lsi.cad,comp.sys.encore
Subject: Request for info on Parallel Discrete Event Simulation
Message-ID: <2949@minyos.xx.rmit.oz>
Date: 19 Feb 90 07:01:34 GMT
Sender: news@minyos.xx.rmit.oz
Followup-To: comp.lsi.cad
Lines: 39


I am doing research into parallel logic simulation for vlsi cad work,
in particular parallel discrete event simulation. I would like to hear
from anyone who may be able to help with information on the following
topics ... 

	- parallel discrete event simulation including theoretical and
	  practical studies/implementations
	- vlsi logic (digital) simulation statistics
	  (eg how much available concurrency is there ?)
	- partitioning strategies and other heuristics used in parallel
	  simulation schemes
	  (eg how to partition a circuit to be simulated for minimum
	  overheads and maximum concurrency )
	- specialised parallel simulation hardware (esp. as applied to
	  discrete event simulation)
	- sparse matrix evaluation for circuit simulation on parallel
	  machines (if applicable to digital simulation)
	- previous surveys/literature reviews on this topic
	- the names of conferences, journals, etc. to look in

I know of at least one implementation of PDES (on an Encore) but it was
a large grain simulation (of a computer system). What I really need to
know is a) whether it is viable/worthwhile to use PDES for vlsi layouts,
	b) what sort of architecture(s) is required to make it practical.

Mailed responses would be appreciated, I will summarise the information
for those interested.

TIA,
	Mark

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| Mark Rawling,	CSIRO Parallel Systems Architecture Project		       |
|		c/o Royal Melbourne Institute of Technology,		       |
|		124 Latrobe St, Melbourne, 3000, Aus.			       | 
|		phone: (+ 61 3) 660 2726				       |
| 		email: rcomr@koel.co.rmit.oz{.au}			       |
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