Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!yale!cmcl2!lanl!opus!jthomas
From: jthomas@nmsu.edu (James Thomas)
Newsgroups: comp.sys.hp
Subject: HP PA assembly language question
Message-ID: <564@opus.NMSU.EDU>
Date: 5 Mar 90 21:48:55 GMT
Sender: news@nmsu.edu
Organization: NMSU Computer Science
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I'm an old CISC hacker trying to understand the PA and some of the choices
made in its design :-)

In the HP Precision Architecture Handbook (I have June 1987), on page 5-59,
there is a description of a normal intraspace routine call, to wit:

	BL	target,rp			LDIL	L%target,rp
	BLE	R%target(GRr,rp)
	OR	GR31,0,rp

.  Now, I understand the other version with the LDIL, but I am stymied by
the two branches version.

1)  I assume that "GRr" is supposed to be "SR4".  The first register in the
() is a space register name, not a general purpose register name, no?

2)  How can a branch be equivalent to a load?  As I understand it, the
given sequence of instructions ought to have the following effect:

	BL	target,rp
				a) target is used as a relative address to
				   provide the next instruction address
				   for after the delay slot (if target is
				   more than 256K away, this gets an
				   assembly or link error)
				b) .+8 is put in rp (assuming a non-branch
				   instruction preceeded)
	BLE	R%target(SR4,rp)
				a) this is in the delay slot of the BL
				b) .+4+"the 11 low order bits of target"
				   provide the next instruction address
				   for after the delay slot
				c) target+4 is put in rp
	instruction at target is executed
				a) this is in the delay slot of the BLE
				b) ???
	instruction at some rather random address is executed
				a) whatever was branched to by the BLE

, and the OR is ignored.

What is wrong with the above picture?  Would some PA guru please fill in my
understanding delay slot?

Thank you.
Jim Thomas	9000/840 @ midas!jthomas@wsmr-emh82.army.mil