Path: utzoo!attcan!uunet!husc6!bu.edu!mirror!prism!rob
From: rob@prism.TMC.COM
Newsgroups: comp.sys.ibm.pc
Subject: Re: Interrupt question
Message-ID: <206900170@prism>
Date: 2 Mar 90 20:52:00 GMT
References: <140700021@cdp>
Lines: 33
Nf-ID: #R:cdp:140700021:prism:206900170:000:1576
Nf-From: prism.TMC.COM!rob    Mar  2 15:52:00 1990


jim@cdp.UUCP asks:

>Does anyone have any information on exactly (in excruciating detail)
>what happens after the CPU receives a hardware interrupt and before the time
>the interrupt handler is entered.  In what order do context saves,
>etc. happen?  In what order to registers get put on the stack?  What
>else goes on the stack and in what order?  Any information or a
>pointer to a detailed discussion of this subject would be greatly
>appreciated.  The environment is PC-DOS v3.3.

   Any of the Intel reference manuals for the 8086 line would have
detailed information on this subject. In brief (assuming the interrupt 
enable flag is set) the CPU

   1) waits for the current instruction to complete.
   2) issues two interrupt acknowledge cycles
   3) reads a byte from the bus indicating which interrupt is being requested
      (this byte should be placed on the bus by the requesting device, usually
      an interrupt controller, during the second INTA cycle)   
   4) Looks up the handler address in the interrupt table (the above
      byte, multiplied by 4, provides the offset into the table)
   5) Pushes the flags onto the stack
   6) Clears the interrupt enable and trap flags
   7) Pushes CS onto the stack
   8) Loads CS with the segment address of the interrupt handler
   9) Pushes IP onto the stack
  10) Loads IP with the offset address of the interrupt handler

   At this point, the transfer to the handler is complete.

   Non-maskable interrupts are a bit different; the state if the interrupt 
flag is ignored, and the handler is always vector 2.