Path: utzoo!attcan!lsuc!maccs!cs4g6ag
From: cs4g6ag@maccs.dcss.mcmaster.ca (Stephen M. Dunn)
Newsgroups: comp.sys.ibm.pc
Subject: Re: Brain-dead 286 - summary
Message-ID: <25F9E445.20494@maccs.dcss.mcmaster.ca>
Date: 11 Mar 90 05:38:12 GMT
References: <8681@rosevax.Rosemount.COM> <29405@amdcad.AMD.COM> <38299@iuvax.cs.indiana.edu> <9982@portia.Stanford.EDU>
Reply-To: cs4g6ag@maccs.dcss.mcmaster.ca (Stephen M. Dunn)
Distribution: na
Organization: McMaster University, Hamilton, Ontario
Lines: 18

In article <9982@portia.Stanford.EDU> dhinds@portia.Stanford.EDU (David Hinds) writes:
$ [...] A 20MHz 386 can still work at
$"near 0 wait states" with interleaved memory.  At higher speeds, a static
$RAM cache is necessary for avoiding wait states.  I don't know if there are
$cache controllers for the 286, but I'm pretty sure the Intel cache controller
$only works with 386's.

   I can't comment on what systems Intel's cache controller works with,
but don't forget that there were 386s with caches before Intel came up with
the cache controller.  These were designed and implemented as custom
silicon, and the same can be done for the 286.  Of course, it's so much
easier to use a ready-made cache controller ...

-- 
Stephen M. Dunn                               cs4g6ag@maccs.dcss.mcmaster.ca
          <std_disclaimer.h> = "\nI'm only an undergraduate!!!\n";
****************************************************************************
    "So sorry, I never meant to break your heart ... but you broke mine."