Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!tut.cis.ohio-state.edu!ucbvax!bloom-beacon!bu.edu!mirror!rob From: rob@mirror.tmc.com (Rob Limbert) Newsgroups: comp.sys.ibm.pc Subject: Re: Brain-dead 286 - summary Message-ID: <37640@mirror.tmc.com> Date: 14 Mar 90 17:33:12 GMT Reply-To: rob@prism.TMC.COM (Rob Limbert) Lines: 33 In article <38483@iuvax.cs.indiana.edu> sl197009@silver.ucs.indiana.edu (Chima Echeruo) writes: >>In article <9982@portia.Stanford.EDU> dhinds@portia.Stanford.EDU (David Hinds) writes: >>$ [...] A 20MHz 386 can still work at >>$"near 0 wait states" with interleaved memory. At higher speeds, a static >>$RAM cache is necessary for avoiding wait states. I don't know if there are >>$cache controllers for the 286, but I'm pretty sure the Intel cache >>$controller only works with 386's. >My 20Mhz 286 which is based on the Chips & Tech NEAT chipset claims ZERO >wait state performance using interleaved memory. Norton SI = 22.5 The key word here is 'claims'. It's common practice to advertise fast 286, 386, and 486 machines as having 0 wait states when they actually don't. Of course, the phrase 'zero wait state performance', which shows up in ads a lot, is vague enough that it doesn't mean much. Most of the more complex memory architectures (caching, interleaving, etc.) work by allowing 0 wait states under certain conditions, and >0 wait states under others. Thus the only really meaningful figure is an average for a supposedly typical code sequence. A good cache controller will offer 0 wait states perhaps 95% of the time, and 4 or 5 wait states (for cache misses) the rest of the time, for an average of around 0.2 wait states. A typical interleaved system might work with 0 wait states 50% of the time, and 2 wait states the other 50%, for an average of about 1. Running a 20Mhz or faster machine completely without wait states would require using very fast DRAM or SRAM for main memory, and would be prohibitively expensive. By the way, though Intel doesn't make a cache controller for the 286, there's nothing that prevents a 286 from being cached. 286 based accelerator boards have been using caches for years, and some faster 286 machines use caches.