Path: utzoo!utgpu!news-server.csri.toronto.edu!clyde.concordia.ca!mcgill-vision!bloom-beacon!snorkelwacker!think!samsung!cs.utexas.edu!sun-barr!newstop!sun!shukra!ram
From: ram@shukra.Sun.COM (Renu Raman)
Newsgroups: comp.sys.m88k
Subject: Re: What the heck is "instruction folding"?
Message-ID: <132876@sun.Eng.Sun.COM>
Date: 13 Mar 90 21:32:33 GMT
References: <25FAED94.24113@paris.ics.uci.edu>
Sender: news@sun.Eng.Sun.COM
Reply-To: ram@sun.UUCP (Renu Raman)
Organization: Sun Microsystems, Mountain View
Lines: 46

In article <25FAED94.24113@paris.ics.uci.edu> rfg@paris.ics.uci.edu (Ronald Guilmette) writes:
>The following is a short excerpt from the March 1990 issue of Unix Review
>(page 26):
>
>	In December 1989, Dolphin { Server Technology } announced the Orion,
>	a project that is to take performance far beyond today's 88k
>	processors by building a processor using the 88k instruction set
>	that is capable of executing up to eight instructions in parallel
>	to achieve a theoretical peak performance of 1000 MIPS.  Dolphin
>	Marketing Manager Lars Lauritzsen says the ECL processor uses a
>	patented technique that the company calls "instruction folding",
>	a result of Norsk's research in improving performance.
>
>...and later on...
>
>	... the Orion processor should ship in the first half of 1992.
>	Orion is the subject of a mutual exchange of patented technology
>	between Dolphin and Motorola.
>
>I wonder what this is all about.  Perhaps someone reading this can enlighten
>me.
>
>I understand that it might make sense to make a VLIW version of an 88k,
>but what is this "instruction folding" stuff all about?  That's a new one
>on me!  Is it just marketing hype or is there really something novel here?
>
>Since the claim is made that is it already patented, I can't see any
>reason for undue secrecy.  Perhaps one of the many Motorola engineers
>who reads this newsgroup on a regular basis will enlighten us all about
>"instruction folding".
>
>// rfg

    If an instruction does not occupy a pipeline slot, then one says "<that>
    instruction is folded", for e.g,  Floating-point ops can be detected
    or pre-decoded say in some small I-cache or pre-fetch queues and shipped
    to the FP controller directly without entering the main integer pipeline.
    This saves 1 pipe-line slot and in-effect increases your instruction
    bandwidth requirements and reduces your FP instruction's start to result
    latency.  Then one says "Floatint point folding". Likewise
    one can say about branches, which is called "branch folding" and I am 
    guessing Moto marketing has generalized it to "Instruction folding" -
   Renukanthan Raman				ARPA:ram@sun.com
   Sun Microsystems			UUCP:{ucbvax,seismo,hplabs}!sun!ram
   M/S 18-412, 2500 Garcia Avenue,               TEL:415-336-1813
   Mt. View,  CA 94043